Tom's Hardware on MSN

New 3D-stacked memory tech seeks to dethrone HBM in AI inference — d-Matrix claims 3DIMC will be 10x faster and 10x more efficient

Santa Clara-based startup d-Matrix looks to replace HBM in AI inference with 3DIMC, or 3D digital in-memory-compute. The ...
Semiconductor Engineering

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems

“Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield ...
Design-Reuse

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
Compound Semiconductor

STARLight Project chosen as European photonics consortium

STARLight, selected by the European Commission under the EU CHIPS Joint Undertaking, aims to develop application-driven ...
EurekAlert!

Small microring array enables large complex-valued matrix multiplication

Optical computing uses photons instead of electrons to perform computations, which can significantly increase the speed and energy efficiency of computations by overcoming the inherent limitations of ...

Academic Frontiers | Breakthrough High-Precision Photonic Computing: Automated Setting Technology of Mach-Zehnder Interferometers

Keywords: Mach-Zehnder Interferometer, Optical Computing, High-Precision Control In an era where electronic hardware faces power consumption, bandwidth, and latency bottlenecks, photonic technology is ...
insideHPC

Sparse Matrix Multiplication

Sparse matrix computations are prevalent in many scientific and technical applications. In many simulation applications, the solving of the sparse matrix-vector multiplication (SpMV) is critical for ...