Smaller is better when it comes to sterile device package design. The EtO package design is generally either a Tyvek lidded thermoform tray, a Tyvek-poly film pouch, or, for moisture- and ...
TEMPE, AZ--(Marketwire - Oct 22, 2012) - EPEPS -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced enhancements to its Allegro ® 16.6 ...
Three independent design processes – chip, package, and PCB – are typically required for the latest electronic products which utilize increasingly complex systems on chip (SoCs) and multiple chips in ...
Don't be so stuck in the circuits that you forget the importance of IC packages. Here are a couple cards from the Microchip 2005 product selector: While most design engineers are using surface mount ...
As system-on-chip designs migrate to nanometer silicon, packaging technology is challenged to keep pace with the integration and performance capabilities offered. Nowhere is this more so than in ...
The use of FinFET devices in next-generation high-performance, low-power designs is a fundamental shift that is happening in the semiconductor industry. These devices through their smaller sizes, ...
As the speeds of various SerDes interfaces move into the multi-gigabits/sec range, more ASIC chips are being designed to have multiple high speed interfaces such as USB 3.0, PCIE Gen3, DDR3, and ...
Concurrent design of a chip and its packaging environment is becoming more important than ever for several reasons. Designing a large, high power die, e.g. a System-on-Chip (SoC), without considering ...
Originally, I started to write this entry about a Sustainable Brand Identity. But as I put pen to paper and fingers to keyboard, I realized that my opening paragraph deserved a bit more attention.
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